The present invention relates to an improvement of a color television receiver having an automatic white control circuit.
In a conventional color television receiver of an NTSC television system, a reference white color temperature of a CRT is set to be 6,774 K, for example. The reference white of the color temperature is the basis for color reproduction. Deviation between the CRT reference white color temperature and the color temperature of 6,774 K results in a color misregistration between the original color of a photographed object and the color reproduced by the television receiver. Therefore, the reference white must be accurately maintained at a predetermined value.
A color CRT of the color television receiver is driven by red (R), green (G) and blue (B) signal components extracted from a composite color television signal. The CRT drive levels at the R, G and B electron guns in response to the R, G and B signal components must be accurately set at predetermined levels in order to determine reference white. When the drive biases of the respective electron guns deviate from prescribed values, an adverse effect such as a cutoff error (deviation in cutoff level) of the color CRT occurs. The cutoff error is caused by a deteriotation in electron emission of the CRT cathode due to aging and/or caused by a drift of the operating point of associated circuitries. Accordingly, a color television receiver is generally provided with a means for adjusting the bias of the CRT in order to eliminate disadvantages due to the cutoff error.
The above bias adjusting means conventionally includes an electronic circuit with a service switch. The service switch has two switching positions. One is a "service position" and the other is a "normal position". When the service switch selects the service position, the CRT is off-circuited from a video signal and the vertical scanning is stopped. In this state, each cutoff voltage of electron guns of the CRT is set at a given value by adjusting each bias of the electron guns. Then, the CRT is properly cut off at the black level of the video signal, and the relative amplitude ratio among chrominance signals throughout the entire luminance level is properly maintained. When the bias adjustment is completed, gains of CRT drivers coupled to the respective electron guns are adjusted to predetermined values. As a result, the amplitude ratio among the R, G and B drive signals in the normal operation of the CRT becomes optimal.
The above-mentioned adjustment requires skill and experience. It is quite hard for general users to complete the above adjustment at home. When the color television receivers are used for a long period of time, the reference white becomes deviated from the prescribed value, resulting in unnatural color reproduction.
An automatic white control circuit has been recently proposed to automatically adjust the reference white even if a deterioration in the CRT cathode emission and an operating point drift in the associated circuitries occur. A typical example of such a white control circuit is shown in FIG. 1.
Referring to FIG. 1, a reference numeral 10 denotes an antenna. A television signal caught by antenna 10 is fed to a television signal processing circuit 11. Circuit 11 is generally formed of a tuner, PIF circuit, video detector, amplifier, chrominance/luminance separator, sync separator, etc. Color difference signals EllR, EllG and EllB for R-Y, G-Y and B-Y respectively appear at output terminals 11R, 11G and 11B of circuit 11. Signals E11R, E11G and E11B are supplied to matrix circuits 12R, 12G and 12G, respectively.
A video signal E11Y including a luminance signal -Y which appears at an output terminal 11Y of circuit 11. Signal E11Y is supplied via a mixer 13 to matrix circuits 12R, 12G and 12B. In circuits 12R, 12G and 12B, luminance signal -Y is mixed with color difference signals E11R, E11G and E11B (R-Y, G-Y and B-Y) to produce chrominance signals E12R, E12G and E12B for R, G and B, respectively.
A blanking signal E11S containing blanking pulses BLK appears at an output terminal 11S of circuit 11. Signal E11S is supplied to a pulse separator 14. In separator 14, blanking pulses BLK are separated into a vertical blanking pulse E14V and horizontal blanking pulse E14H. Vertical and horizontal blanking pulses E14V and E14H are supplied to vertical and horizontal blanking pulse shapers 15 and 16, respectively. Shaper 15 supplies a signal E15 containing a wave-shaped vertical blanking pulse VB to a signal generator 17. Shaper 16 supplies a signal E16 containing a wave-shaped horizontal blanking pulse HB to generator 17.
A reference insertion pulse E17A appears at an output terminal 17A of generator 17. Pulse E17A is supplied to mixer 13. In mixer 13, pulse E17A is inserted in a given part, excluding a picture signal interval, of one horizontal period of video signal E11Y. The inserted reference insertion pulse E17A is supplied, together with luminance signal -Y, to matrix circuits 12R, 12G and 12B.
Chrominance signals E12R, E12G and E12B outputted from matrix circuits 12R, 12G and 12B are supplied to cathodes 21R, 21G and 21B of a color CRT 21 via level correction circuits 18R, 18G and 18B, CRT drivers 19R, 19G and 19B, and output circuits 20R, 20G and 20B, respectively. DC levels of output signals E18R, E18G and E18B from circuits 18R, 18G and 18B are increased or decreased according to DC control voltages E35R, E35G and E35B. These voltages E35R, E35G and E35B are respectively supplied to control terminals 22, 23 and 24 of circuits 18R, 18G and 18B.
Hereinafter, CRT drivers 19R, 19G and 19B are represented schematically by CRT driver 19B. CRT driver 19B is formed of an NPN transistor 25. The base of transistor 25 receives signal E18B from level correction circuit 18B. The collector of transistor 25 is coupled via a resistor 26 to a positive voltage source Vcc, and the emitter thereof is circuit-grounded via a resistor 27. An output signal E19B from the collector of transistor 25 is supplied to output circuit 20B. The circuit arrangement of CRT drivers 19R and 19G may be the same as that of CRT driver 19B.
Output circuits 20R, 20G and 20B are similarly represented by output circuit 20B. Output circuit 20B includes a PNP transistor 28 whose base receives a signal E19B from the collector of transistor 25. The collector of transistor 28 is circuit-grounded via a resistor 29, and the emitter thereof is connected to cathode 21B of CRT 21. When the current amplification factor h.sub.FE of transistor 28 is far larger than "1", a cathode current I21B flowing from cathode 21B into the emitter of transistor 28 is substantially the same as the collector current of transistor 28. In this case, the voltage drop across resistor 29 directly corresponds to the cathode current I21B. Thus, resistor 29 serves as a current detecting resistor. The arrangement of circuits 20R and 20G may be the same as that of circuit 20B.
A signal E20B corresponding to the voltage drop at resistor 29 is supplied to a sampling circuit 33B. Signals E20R and E20G being proportional to cathode currents I21R and I21G of CRT 21 are similarly supplied from circuits 20R and 20G to sampling circuits 33R and 33G, respectively. Circuits 33R, 33G and 33B may be conventional sample/hold circuits. Each of sampling circuits 33R, 33G and 33B receives a gate pulse E17B obtained from an output terminal 17B of signal generator 17. Gate pulse E17B is generated in synchronism with the generation timing of reference insertion pulse E17A (a detailed description regarding the generation timing of E17A and E17B will be made later with reference to the timing chart of FIGS. 2A to 2E).
Sampling circuit 33R samples the DC potential of signal E20R at the duration of reference insertion pulse E17A, and holds the sampled potential to provide a sampling output signal E33R. Sampling circuit 33G samples the DC potential of signal E20G at the duration of pulse E17A, and holds the sampled potential to provide a sampling output signal E33G. Sampling circuit 33B samples the DC potential of signal E20B at the duration of pulse E17A, and holds the sampled potential to provide a sampling output signal E33B.
Sampling output signals E33R, E33G and E33B are supplied to respective negative inputs (-) of comparators 35R, 35G and 35B. Each positive input (+) of comparators 35R, 35G and 35B receives a reference potential E1 from a reference potential source 36. Comparators 35R, 35G and 35B respectively supply DC control voltages E35R, E35G and E35B to control terminals 22, 23 and 24 of level correction circuits 18R, 18G and 18B. Then, three independent negative feedback control loops for R, G and B are formed. DC control voltages E35R, E35G and E35B from comparators 35R, 35G and 35B increase when the potentials of sampling output signals E33R, E33G and E33B become lower than reference potential E1. Voltages E35R, E35G and E35B decrease when the potentials of signals E33R, E33G and E33B become higher than reference potential E1. DC control voltages E35R, E35G and E35B are converged to certain values by the DC negative feedback operation when the differences between the reference potential E1 and the respective potentials of signals E33R, E33G and E33B become zero.
Incidentally, a high voltage is applied to the anode of CRT 21 via an anode cap 40. Horizontal and vertical deflection currents are supplied via terminals 42 and 43 to a deflection coil 41. Other non-essential parts for the present invention, such as an audio circuit etc., are not illustrated.
The automatic white control circuit of FIG. 1 will operate as follows.
FIG. 2A shows a typical waveform of video signal E11Y from terminal 11Y of television signal processing circuit 11. In FIG. 2A, reference symbol VB denotes a vertical blanking pulse; HB denotes a horizontal blanking pulse; and L denotes a picture signal. FIG. 2B shows a waveform of signal E15 from vertical blanking pulse shaper 15, and FIG. 2C shows a waveform of signal E16 from horizontal blanking pulse shaper 16. Blanking pulses VB and HB shown in FIGS. 2B and 2C are supplied to signal generator 17. Reference insertion pulse E17A shown in FIG. 2D appears at output terminal 17A of signal generator 17. Pulse E17A is generated, excluding the period of picture signal L, within an interval (T1) of horizontal blanking pulse HB. Pulse E17A can be easily obtained by a conventional counter circuit with a proper gate circuit. Pulse E17A (FIG. 2D) is mixed in mixer 13 with video signal E11Y (FIG. 2A), so that a composite signal E13 (FIG. 2E) is obtained. Composite signal E13 is supplied to the respective cathodes of CRT 21 via circuit elements 12, 18, 19 and 20.
In the following description, the operation regarding the blue circuit elements represents each operation of the red, green and blue circuit elements.
Cathode current I21B from cathode 21B of CRT 21 flows into resistor 29 through the emitter-collector path of transistor 28. Resistor 29 provides a voltage drop corresponding to the magnitude of cathode current I21B, and signal E20B having a potential corresponding to the above voltage drop appears at the node between resistor 29 and the collector of transistor 28. Signal E20B is then supplied to sampling circuit 33B. Circuit 33B receives gate pulse E17B in synchronism with the generation (period T1) of reference insertion pulse E17A. Gate pulse E17B determines the timing of sampling and holding operations in circuit 33B. Sampling circuit 33B samples the potential of signal E20B and holds the sampled potential in a capacitor Cb. The sampled and held signal E33B is supplied to the negative input (-) of comparator 35B.
Comparator 35B has a characteristic as shown in FIG. 3. When the reference potential applied to the positive input (+) of comparator 35B is given to be E1 and the input and output potentials of comparator 35B are respectively plotted along the abscissa and ordinate, the output potential (E35B) decreases as the input potential (E33B) increases.
Level correction circuit 18B has such an electrical characteristic that the output DC level of signal E18B raises when DC control voltage E35B applied to control terminal 24 increases, while the output DC level of E18B falls when E35B decreases.
When the emission of cathode 21B is deteriorated (or a certain drift in the operating point of associated circuitries occurs), the corresponding cathode current I21B flowing into resistor 29 of circuit 20B becomes small. The potential of signal E33B from sampling circuit 33B is proportional to the magnitude of cathode current I21B which is obtained at the period of reference insertion pulse E17A (FIG. 2D). Since the sampling is performed only during the period T1 of reference insertion pulse E17A, the potential of signal E33B is independent of the period of picture signal L. Thus, when the deterioration of cathode emission occurs, the sampled output E33B is decreased regardless of the presence of any picture signal L.
Comparator 35B compares reference potential E1 with the potential of sampled output E33B. When a deterioration of the cathode emission occurs, comparator 35B generates DC control voltage E35B which is increased in accordance with the characteristic of FIG. 3. Then, the DC level of signal E18B from level correction circuit 18B is increased, thereby increasing the corresponding cathode current I21B.
On the contrary, when the cathode current increases, operation opposite to the operation described above is performed so as to decrease the corresponding cathode current. The increase/decrease operation point of the negative feedback control is stably converged to a point at which the difference between the reference potential E1 and the sampled output E33B becomes zero.
The cathode emission correction operation for R and G components may be performed in the same manner as that for the B component as described above. When the negative feedback control circuit is arranged to set the difference between the reference potential (E1) and the sampled output (E33) to be zero while the initial reference white is properly adjusted, the CRT biases for R, G, and B are automatically adjusted even if a deterioration in the cathode emission of CRT or a drift in the operating point of associated circuitries occurs. As a result, an automatic correction is so performed that the reference white is always maintained at a predetermined value.
In a color television receiver having the automatic white control circuit described above, no problem occurs in normal operation. However, when the power of a color television receiver has been switched off for a long period of time, the temperature at each cathode of a CRT is substantially the same as room temperature. When the power of a color television receiver is switched on under this condition, a certain period of time (generally several seconds) is required to heat-up the CRT cathode. Unless the CRT cathode is heated up to a sufficient temperature, no cathode emission is obtained and no cathode current flows. As is apparent from the negative feedback operation described before, when no cathode current flows, each potential of outputs from sampling circuits 33R, 33G and 33B becomes minimum. For this reason, the outputs from comparators 35R, 35G and 35B and hence the output DC levels of level correction circuits 18R, 18G and 18B are increased, so that the drive voltage for each cathode of the CRT is fixed at the saturation level of the CRT drive circuits. (In this condition, each cathode potential of the CRT is minimum so as to increase the cathode current because each of the negative feedback loops detects no cathode current.) Under this condition, when each cathode temperature rises over a certain value, each cathode current begins to flow. Then, the drive voltage for the CRT cathode begins to decrease and is converged to a certain given value.
When the power of the above color television receiver is switched on with cool CRT cathodes, a picture is reproduced under the minimum cathode potential so that the raster of CRT always appears with the maximum brightness at the initial period of power-on, thereby shortening the life of CRT, causing deviations in reference white, and discomforting viewers. This is the problem to be solved by the present invention.